Integrated circuits are typically fabricated from one or more layers of different materials. Typical integrated circuits include multiple interconnected patterned metal layers, with intervening inter-level dielectric (ILD) layers to electrically insulate the metal layers.
The selection of a specific ILD depends upon the performance, density and reliability requirements of a particular semiconductor circuit. Ideal ILDs are contamination and defect free, exhibit a low dielectric constant that approaches unity, have a sufficiently high field strength, provide a good barrier to sodium ions (Na+) and provide infinite etch selectivity to underlying materials, such as silicides, silicon and polysilicon. ILDs must also conform to different topographies, such as steps and gaps, exhibit good adhesion to the underlying and overlying layers and be capable of planarization.
Good ILD planarization characteristics become increasingly important as the number of layers in a device increases, because photolithographic processing is acutely sensitive to variations in ILD topography, particularly in accurately forming vias on uneven surfaces. However, in fabricating ultra high density semiconductor devices, which include tightly packed, high aspect ratio metal patterns, it is difficult to satisfactorily planarize a deposited dielectric material. This is particularly true when a layer of circuitry contains both relatively dense areas that contain a relatively large number of circuit components and areas such as peripheral circuit regions, that contain relatively few circuit components, wherein a step or elevation results therebetween.
A conventional approach to forming ILDs involves depositing two dielectric layers. A first dielectric gap fill layer, e.g., spin-on-glass (SOG), silicon dioxide (SiO.sub.2), or other oxide, is deposited on a patterned metal layer to fill any gaps therein. Typical gap fill layers not only fill gaps in the patterned metal layer, but also form a layer on the upper surface of the underlying metal features. Then a second dielectric layer, referred to as a "cap layer," is deposited on the gap fill layer. The cap layer is then planarized (leveled), as by a chemical-mechanical polishing (CMP), to provide a substantially flat upper surface on which additional layers are formed.
ILD structures formed according to conventional methodology typically contain a reasonably flat upper surface but suffer from hot carrier injection (HCI) reliability failures. It is well recognized that HCI problems typically arise when semiconductor device dimensions are reduced while the supply voltage is maintained at the same level, thereby increasing the electric field generated in the silicon substrate. As a result, some electrons in the channel are sufficiently energized to be injected into the gate oxide, charging the gate oxide and causing long term device degradation which raises the threshold voltage of the device. Accordingly, there exists a need for high density multi-level semiconductor devices having adequately planarized ILDs with improved resistance to HCI degradation.